Level converters are frequently used in an electronic circuit to convert the level of logic signals from a region of the circuit which is supplied by a first supply voltage and to forward them to a circuit region which is supplied by another supply voltage. One use of such circuits is in dynamic semiconductor memories (Dynamic Random Access Memories (DRAMs)). In this case, the circuit regions inside the semiconductor memory are operated, for example, with a supply voltage of 1.5 V, while the circuit regions which are arranged on the output side are operated with a supply voltage of 2.1 V.
A fundamental demand imposed on such a level converter is that a logic signal is not delayed as far as possible and a high operating frequency can be complied with. In addition, signal characteristics, in particular the duty ratio of the logic signal to be converted, such as the ratio between the high and low phases of the signal, should not be changed as far as possible.
FIG. 11 shows a conventional level converter. The level converter, which is designed using CMOS technology that is nowadays customary, has two signal paths which are connected between a supply potential connection VDDQ and a reference potential connection VSS. The signal paths each comprise an n-channel field effect transistor N1, N2, whose control connections simultaneously constitute the signal input 101 and 102 of the level converter, and a p-channel field effect transistor P1 and P2 whose control inputs are each cross-coupled to the other signal path. The signal inputs 101 and 102 are used to supply a push-pull signal having a first voltage swing to the level converter, said push-pull signal being composed of a first signal component I1 and a second signal component I2, and the second signal component I2 having a signal level that is complementary to the first signal component I1. The signal paths are thus driven in a complementary manner to one another. Logic signals having a second voltage swing can be tapped off at the outputs 111 and 112 of the level converter.
On account of the customary dimensions of the n-channel and p-channel field effect transistors, the logic levels of the output signals Z1 and Z2 of the level converter are no longer completely complementary to one another. This is illustrated, for example, in FIG. 12 using a signal/time diagram of the input and output signals of the level converter. The pulsed signals I1 and I2, for instance corresponding to a clock signal in this case, are applied to the inputs 101 and 102 of the level converter. The voltage swing corresponds to the first voltage range in the form of a difference between a first supply voltage VDD and a first reference voltage VSS. The output signals Z1 and Z2 have a second voltage swing which, in accordance with the second voltage range, results as the difference between a second supply voltage VDDQ and a second reference voltage VSSQ.
If the input signal I1 has a rising edge, the level of the output signal Z1 begins to fall after the high level has been reached by the input signal I1, that is to say with a certain delay by the transistor N1. Upon switching in the opposite direction, the p-channel field effect transistor P1 is first of all influenced by the cross-coupling to the other signal path and the output voltage Z1 begins to rise to the high level only after the transistor P1 has been completely switched. This corresponds approximately to a delay by two transistors. A similar situation applies to the derivation of the output signal Z2. In the case of the two output signals Z1 and Z2, the duration of the low level is now clearly longer than the duration of the high level, which corresponds to a change in the duty ratio (duty cycle).
This distortion of the duty ratio may result in the functionality of an integrated circuit being adversely affected, in particular at high switching frequencies. In addition, such a temporal discrepancy can be caused by a prescribed clock signal, so-called jitter.